The present invention relates to an adder which has a high performance and is self-checking without requiring a large amount of circuit overhead.
In data operations of a computer system, the ADD operation is the most frequently performed operation in the data path of the processor unit. The performance (or speed) of this operation mainly depends on the carry propagation scheme implemented in the design of the adder. However, in order to provide a real-time error detection, self-checking of the ADD operation is very desirable in many high reliability systems. For an n-bit ADD operation where n is very large a carry lookahead scheme may be used to reduce the carry propagation delay from n stages to log (n) stages. However, no adder has been previously designed in which high performance and self-checking are accomplished without requiring too large an amount of circuit overhead.
U.S. Pat. No. 4,737,926 (Vo et al.) teaches an implementation of a carry lookahead scheme for adder design. Large bit groups are used in the middle of the lookahead circuit while shorter bit groups are used at the ends to reduce carry propagation delay (e.g., 3-4-5-6-5-4-3-2 bit partition shown in FIG. 5.)
U.S. Pat. No. 4,718,034 (Takla et al.) teaches a carry-save propagation adder implemented using exclusive-OR blocks.
U S. Pat. No. 4,718,035 (Hara et al.) shows a simple circuit in bipolar technology which can perform carry select operation.
U.S. Pat. No. 4,525,797 (Holden); U.S. Pat. No. 4,763,295 (Yamada et al.); U.S. Pat. No. 4,682,303 (Uya): and U.S. Pat. No. 4,845,655 (Yamada et al.) discuss the basic idea of using a carry select scheme, to achieve high performance parallel adding. Circuit implementation and various block partitions are presented as to the carry select adder design.
In all previous carry select schemes (including those mentioned above), carry inputs to adder blocks are constant and the carry generated from each block is only used to select pre-computed sum outputs from a higher-order block. No adder has previously been designed in which both high performance and self-checking are accomplished without requiring too large an amount of circuit overhead.